1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a gate electrode by a semi-damascene process to prevent a metal layer from being oxidized when a gate electrode having a layered structure of the metal layer and a polysilicon layer is formed in a CMOS transistor of a high integrated device such as a DRAM cell.
2. Background of the Related Art
In a prior art method for fabricating a dual gate electrode device, a n.sup.+ gate and a p.sup.+ gate are respectively deposited and patterned on an upper portion of an undoped polysilicon layer using a mask and dual implantation method (n.sup.+ :As.P, p.sup.+ :B.BF.sub.2), or an in-situ doping method.
The dual implantation method has a relatively simple process, but it is difficult to achieve high doping levels. Also, in the dual implantation method, it is likely that gate depletion will occur as a result of the dopant profile characteristics.
In the in-situ doping method it is necessary to set up respective process steps, because the gate electrodes for the n.sup.+ and p.sup.+ polysilicon layers should be formed separately.
A prior art method for fabricating a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1C are sectional views showing prior art process steps for fabricating a semiconductor device.
As shown in FIG. 1A, a device isolation film 12 is formed to define active regions on a semiconductor substrate 10.
A p-type well is formed in a portion where an NMOS device will be formed (NMOS region I), and an n-type well is formed in a portion where a PMOS device will be formed (region II).
Subsequently, a gate insulating film 14 is formed on the upper portion of the entire surface, and a polysilicon layer is formed on the gate insulating film 14. A first photoresist film pattern is then formed on the polysilicon layer to expose the NMOS region I. An n.sup.+ polysilicon layer is formed by an n-type impurity ion implantation using the first photoresist film pattern as an ion implantation mask.
Afterwards, the first photoresist film pattern is removed. A second photoresist film pattern is then formed on the polysilicon layer to expose the PMOS region II. A p.sup.+ polysilicon layer 16a is formed by a p-type impurity ion implantation using the second photoresist film pattern as an ion implantation mask. Then, the second photoresist film pattern is removed.
Next, a diffusion prevention film 18a, a metal layer 20a, and a mask insulating film 22a are sequentially formed on the upper portion of the entire surface to form a layered structure.
As shown in FIG. 1B, the layered structure and the polysilicon layer into which the impurity ions were implanted are etched using a gate electrode mask that which protects a portion where a gate electrode will be formed as an etching mask. Thus, a mask insulating pattern 22b, a metal layer pattern 20b, a diffusion prevention film pattern 18b, an n.sup.+ gate electrode 15b, and a p.sup.+ gate electrode 16b are formed.
Afterwards, the n.sup.+ gate electrode 15b, the p.sup.+ gate electrode 16b, and the exposed semiconductor substrate 10 are selectively oxidized to form a buffer insulating film 24.
Subsequently, a mask process is respectively performed in the NMOS region I and the PMOS region II, so that a lightly doped impurity ion implants can be made into the NMOS region I and the PMOS region II. Thus, an n-LDD region 26a and a p-LDD region 26b are formed.
As shown in FIG. 1C, a double structure of an oxide film spacer 28 and a nitride film spacer 30 is formed at the sidewalls of the mask insulating film pattern 22b, the metal layer pattern 20b, the diffusion prevention film pattern 18b, and the n.sup.+ gate electrode 15b the p.sup.+ gate electrode 16b respectively.
Subsequently, a mask process is respectively performed in the NMOS region I and the PMOS region II, so that a heavily doped impurity ion is implanted into the NMOS region I and the PMOS region II. Thus, an n.sup.+ source/drain region 27a and a p.sup.+ source/drain region 27b are formed. The nitride film spacer 30 will act as an etching barrier in a later self-aligned contact process.
Afterwards, an interlayer insulating film 32 is formed on the upper portion of the entire surface and then planarized.
The aforementioned related art method for fabricating a semiconductor device has several problems.
The metal layer pattern constituting the gate electrode expands during later annealing processes. The metal layer pattern also expands due to etching selectivity differences between the mask insulating film and the metal layer pattern during etching process for forming the gate electrode. For this reason, the impurity ion is not implanted into a corner portion of the gate electrode during the subsequent ion implantation process for forming the LDD regions. Furthermore, lifting of the gate electrode can occur due to oxidation of the metal layer pattern. This deteriorates the device characteristics, yield and reliability.